SystemVerilog Clocking Block
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Input and Output Skew
A skew number for an input denotes when that input is sampled before the
clocking event (such as posedge or negedge) occurs. For an output, it is just
the opposite - it denotes when an output is synchronized and sent after
the clocking event.
1step
A 1step is a special unit of time. It denotes a negative time delay
from the edge of a clock when all inputs are steady and ready to be sampled.
In terms of scheduling semantics, a 1step unit denotes the Postponed region
immediately before a clock edge.
Default input and output skews
The default skew statement in the above example is optional. A clocking block
without this statement (as shown below) is still legal.
clocking clock1 @(posedge clk1);
input a1, a2;
output b1;
endclocking
In this case, the default input skew is 1step and the default output
skew is 0.
Overwriting default skews
Even if there is a default statement for skews in a clocking block, it can be
overwritten later in the block. For example, the example below overwrites the
default input skew for signal a1 (to 1step) and output b1 (to
5 ns), but the input skew for a2 remains unchanged at 2 ns.
clocking clock1 @(posedge clk1);
default input #2ns output #3ns;
input #1step a1;
input a2;
output #5ns b1;
endclocking
Skew value of #0
A skew value of #0 changes the way input values are sampled and output values
are synchronized, even though both will still be done at the simulation time
when a clock event occurs. A skew value of #0 for any input means that the
input will be sampled at the Observed region. An output skew value of
#0 indicates that the output will be synchronized out in the Non-blocking
assignment (NBA) region.
Parameterized skew value
Skew value (or values) in a clocking block is parameterizable. The following
exampleshows this.
clocking clock1 @(posedge clk1);
parameter INPUT_SKEW = 2;
parameter OUTPUT_SKEW = 3;
default input #INPUT_SKEW output #OUTPUT_SKEW;
input #1step a1;
input a2;
output #5ns b1;
endclocking
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