SystemVerilog Cover Properties

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The property definition, of course does not do anything unless you attach a meaning to it - in this case the coverage. This is done by associating the keyword 'cover' to it.

c1: cover property fifo_nearly_full_p (rst, clk, fifo_nearly_full);

How does it work? Your simulator counts each time the property is attempted (in this case at every positive edge of the clock) and each time the condition (fifo_nearly_full) is true. At then end of the simulation it will produce a report that summarizes the result.

Lastly, since this code will not be synthesized even though it is in RTL, we need to specify that. A clean way of doing this is to put all property and cover property statements in a separate file (say, top_fifo.sva) and include the file in your design.

// synopsys translate_off

`include top_fifo.sva

// synopsys translate_on

Where can I put a cover property?

A cover property can be put in a number of different places.

1. You can use a cover property inside an initial block.

initial begin
   ...
   cover property fifo_nearly_full_p (rst, clk, fifo_nearly_full);
   ...
end 

In such case, the cover property will be checked only for the first positive edge of the clock after time 0 and then it is never checked again.

Prev: Introduction | Next: More places to put cover properties