SystemVerilog DPI Tutorial

Representation of the Basic Types

The correlation between some of the C and SystemVerilog data types are quite intuitive. For instance, it is not hard to see that Verilog integer (or SystemVerilog int) and C data type int are equivalent. As it turns out, most of the SystemVerilog data types, in fact, have C counterparts. This relationship is shown in the table below.

SystemVerilog Type	C Type		SystemVerilog Type	C Type
byte	char		shortint	short int
int	int		longint	long long
real	double		shortreal	float
chandle	void*		string	char*
bit	unsigned char		logic	unsigned char

Can I Map All C Data Types to SystemVerilog?

While the above table is a convenient way of mapping between C and SystemVerilog types, there are other SystemVerilog data types, for which the mapping is little more involved. So, the question is: what are these cases, when mapping between the two domains are not so straight forward?

The first of these cases is related to the enumerated type variable in SystemVerilog. After passing through the interface, the data type becomes the base data type that the enumerated type had. The enumerated name is not available on the C side.

Next, and perhaps the most important of the data types with undefined mapping is the packed data types. Before we go into that here are some quick overviews of the packed and unpacked data types.

Packed and Unpacked Data types - Why Do I need to Know Them?

A packed array, simply put, is a variable that has a dimension declared before the object name.

 
bit [ 7:0] tagPacked;
reg [15:0] accPacked;

An unpacked array has a dimension declared after the object name.

bit tagUnpacked [ 7:0];
reg accUnpacked [15:0];

Of course, there may be arrays that have both packed and unpacked dimensions. A common example of this will be Verilog memories. A convenient way of looking into this is to imagine them as an unpacked array of packed arrays.

 
reg [7:0] memory [15:0];

 
reg [3:0][7:0] convoluted_memory [15:0][23:0];

There are important differences in the ways a simulator handles a packed type versus an unpacked type. A packed array (either as a separate entity or an element of an unpacked array) is treated as a vector. A vector can be used as a single entity in an arithmetic operation (e.g., tagPacked >= tagPacked + 1'b1;) and all bits of a vector is guaranteed to be contiguous. This increases overall simulation performance.

Unpacked data types can be represented as an open array in an operation or as an argument, once the dimensions of the array is properly defined. An open array, denoted by '[]', indicates that the entire array is being used.

   reg accUnpacked [15:0];
   ...
   passing_as_argument(accUnpacked[]);