SystemVerilog Interprocess Synchronization and Communication
[Part 2]
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B. The triggered property
As we have seen already, the task wait() can be used to wait
for an event. Let us look into this in little more details in the
following code.
begin: event_1
...
end
...
wait(event_1);
...
Here, we wait on event_1 and then once that event occurs,
the execution proceeds for rest of the code. Now, what happens
when the wait statement itself occurs at the same time as
event_1? Does the wait unblock or does it wait for the
next event_1? This very commonly occuring race condition
can be resolved using a new property triggered associated
with all event type variables in SystemVerilog. SystemVerilog
defines event_1.triggered to be TRUE throughout the
simulation time slot when event_1 triggers (which, by
itself, is undetectable after it happens). Using triggered
property, the above code can be re-written as:
begin: event_1
...
end
...
wait(event_1.triggered);
...
SystemVerilog lets you play more with the event type variables. If
you have two event type variables event1 and event2,
you can:
- Assign one to the other:
event1 = event2;
In this case, event1 is said to have merged
with event2.
- Reclaim an event:
An event type variable can be 'reset', by assigning a null
value to it.
event = null;
- Compare two events:
Usual comparison operators (==, != and ===) can be used to compare
an event with another event or null.
event1 = null;
Another new feature of SystemVerilog wait_order() is discussed
in details on the next page.
Previous: SV events | Next: wait_order()
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