SystemVerilog Interprocess Synchronization and Communication

[Part 2]

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Event Sequencing: wait_event()

One shortcoming of regular Verilog style wait() statement is that, in stead of waiting for one event, if you need to wait for a sequence of events, there is no straightforward way of doing this.

For example, suppose you want to wait for the event w, followed by the event a, then i, and lastly, the event t. You only want to detect and wait for the events in that order, so any other sequence, such as w, t, a, i, will not satisfy you.

One way of implementing this in traditional Verilog will be to construct a state machine that waits for that sequence of events.

In SystemVerilog, in stead of that, you can use the wait_order(event_list) command to do the same.

   wait_order (w, a, i, t)
      $display("The sequence w, a, i, t occured");

Now what will happen if the events do not occur in the same order as specified (for example, w, t, a, i)?

In such cases, wait_order(w, a, i, t) fails and you can specify an else statement that will be executed after such failures.

   wait_order(w, a, i, t)
      $display("The sequence w, a, i, t occured");
      $display("The sequence w, a, i, t did not occur");

Another interesting situation is ehn the event w occurs, followed by the event a, but then w occurs again. Will wait_order(w, a, i, t) go back and wait for a again? The answer is 'no'. Regardless of how many times the previously occurred events, such as w, occur again, the wait_order() will only wait for the next event, i in this case.

Let us look into a traffic signal example. Suppose G, Y and R represent a signal is turning green, yellow and red respectively. We know for a normal traffic signal, G, Y and R must occur in that sequence. This enables us to write the following assertion for a traffic controller logic.

   wait_order(G, Y, R);
      $error("Problem in logic"); 

Previous: More on SV events


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