Low Power Design

[Part 1]

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How to solve the Power Puzzle? The Power Domain

The only way you can stop the leakage current flowing through a transistor is by shutting down the supply voltage to that transistor. Another way of looking into this would be to shut down the power supply to a block when its operation is non-essential to the overall chip. In order to find the blocks that can be independently made non-operational, you need to answer yourself the following question:

  1. Can the chip be partitioned into independent functionalities that can be made operational or non-operational without affecting one other?
  2. Does a block need to stay ON all the time (perhaps in order to monitor other blocks)?
  3. Is there any signal that runs from a presumably non-operational block to an operational block? As we will see, this does not necessarily make the recipient operational block dependent on the former as long as there is a known or predictable value for the signal when the source block is non-operational.
  4. Can such independent sets of blocks use different voltages? A block that uses lower voltage reduces its overall dynamic power consumption.

Such a set of independent blocks form a Power Domain.

Power domain is the key concept behind solving the low power design and verification challenges. Figure 1 illustrates this. In this example, the logic comprises of three flip flops and some glue logic. (The logic is arbitrary and is created only to illustrate this example). Let us assume that the designer of this logic knows that the operation of the first flop on the left is independent of the others and thus the flop and the associated logic can be shutdown when not needed. Similarly, let us assume that the operation of the entire logic permits the middle flop to be independent also from other two.

Putting this together, we derive the three power domains shown in Figure 2.

What happens when you have power domains with different voltage levels in a design?

In a design containing power domains that operate at different voltage levels, the logic ‘1’ and ‘0’ levels are represented by different voltage levels as well. For instance, the logic ‘1’ and ‘0’ may be represented by 0.9V and 0V respectively in power domain B, whereas, in power domain C, they may be represented by 3V and 0V respectively.

Challenges from the design side:

From the design side, this creates a unique challenge. If there is a signal S1 (see Figure 2) that goes from domain B to domain C, an active high value on that signal (associated with a voltage of 0.9V) will be interpreted as a logic ‘0’ in domain C (assuming the threshold voltage in domain C is somewhere around 1.5 V).

Similarly, a signal S2 going from domain C to domain B which has a logic value of ‘0’ but a voltage value of 0.9V will be interpreted as a logic ‘1’ in domain B.

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