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// PROJECT    VERIPAGE   UPDATE
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// May 9, 2009
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First the housing crisis, then as a result the entire economy tanked and now here is the Swine Flu - is there any end of the cycle? Only time will tell. But as we all go through this, one thing is for sure - you need to be on top of the game and be prepared for the time when things will start getting better. And the only way you can do that is to have the cutting edge knowledge in your field. 

With that note, Project VeriPage is starting a new series this month on Low Power Design. As the technology progresses to smaller geometry, Low Power Design is poised to become the next critical problem to solve. Hope this will be useful for you. 

In this issue:

1. New Article: Low Power Design: Part 1
2. Can you spot the problem?
3. Book of the Month 
4. Are you receiving this from a friend?

- Project VeriPage Team.

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1. New Article: Low Power Design using UPF and CPF: Part 1

You have heard all the buzzwords sorrounding Low Power Design. Here is the definitive tutorial that you do not want to miss. In Part 1 of this tutorial you will learn what motivates low power design and what challenges it poses. 

   <URL: http://www.project-veripage.com/lp_1.php>

As always, this and all other articles on Project VeriPage are free. For complete list of articles, please go to:

   <URL: http://www.project-veripage.com/ >

2. Can you spot the problem?

Vera, the hardworking verification engineer, is trying to create the following assertion. 

   p1: assert property (@(posedge clk) expr disable iff (reset)); 

The assertion fired unexpectedly at time 0. While debugging Vera found that the reset signal was 1'bx for some time after time 0 before it was asserted. After asking around Vera realized the initial time for which the reset signal was X was determined by system design and could not be predicted. How should Vera write the assertion so that it does not fire at time 0?

Tips: 
   (a) You need to know SystemVerilog Assertion (<URL: http://www.project-veripage.com/sva_1.php>).
   (b) Send us your answer to info@project-veripage.com. 
   (c) The answer and the name of the person sending the first correct answer will be published in the next issue of this newsletter.

Answer to last month's puzzle: 
  reg [31:0] cntr; 

  always @(posedge clk) 
    if (rst)  
      cntr <= 0; 
    else  
      cntr <= cntr + 1; 

  always @(negedge rd) 
    dout = cntr; 

Congratulations P Radhakrishnan for sending us the first correct answer to the last month's puzzle!

3. Book of the Month: 

We select "Assertion-Based Design" by Harry D. Foster, Adam C. Krolnik and David J. Lacey as our 'Book of the Month'.

As one reader writes, "Not only that this is the only book on the market that cover important topics like Assertions, this is also well and systematically written book, full of examples in OVL, PSL and SystemVerilog... (This) book is written equally for design and verification engineers, but also for system architects and everybody involved in ASIC development."

You can finger through the book - or if you wish to buy it - from any page of Project VeriPage. 

This and many other recent and classic titles on design and verification are available from our book store - all located at your fingertip at:

   <URL: http://www.project-veripage.com/books.php>

Take a look and remember, books are gifts that last a life time.

4. Are you receiving this from a friend?

If you are receiving this newsletter from a friend, you can get your own copy by subscribing at:

   <URL: http://www.project-veripage.com/list/?p=subscribe&id=1>

And do not let your friends who do not receive this newsletter feel left out! Forward this to your colleague and make their day.

That's all in this issue. Happy design and verification!