SystemVerilog Program Blocks - What, Why and How

Next: Creating Programs

While module has been the primary design entity in Verilog, SystemVerilog introduces few other entities that serve specific purposes. We discuss one such entity, named Program Block, this month.

What are Program Blocks?

The basic syntaxes of Verilog language provide constructs that can be used for both logic design and test benching.

From a language perspective, the primary focus of a design is, of course, how easily the constructs can be synthesized. To make the design work easier, we often build it up as a hierarchy of modules and connect ports of two such modules using nets. Once the hierarchy is correctly built up, the modules can interact with one another.

While you can design a testbench in a similar way (and, indeed, it has been done that waysince from the inception of Verilog), a few minutes of thinking will convince you that the only things that a testbench should care for are:

  • sending input stimulii to the design under test (DUT),
  • receiving and verifying the response for the DUT.
Rest of the ways how a design is implemented - hierarchies, design elements such as registers or pull up wires and so on - have no real significance for a testbench. Following the norms of a design while writing a test bench may significantly increase the turn-around time.

One other problem that often plagues a testbench environment is a race condition between the design and the testbench. Consider the folllwing example. Suppose a testbench is required to wait for a specific response from its DUT. Once it receives the response, at the same simulation time it needs to send a set of stimulii back to the DUT. Since Verilog can execute events in various procedural blocks out-of-order, there is a chance that the testbench may send out the stimulii even before the response from the DUT arrives.

Program block is a recognition of these differences in goals of writing a design and a test bench. It is meant to facilitate writing of a test bench.

A program block is defined within the program and endprogram keyword pair. It serves three purposes.

  • It provides an entry point to the execution of test benches. This is somewhat similar to what a module does for design related constructs.
  • It acts as a scope for data defined within this program block. Once again similar to a module, a program block can act as a scope for encapsulating program wide data.
  • Perhaps the most important aspect of a program block is that it is a syntactic context that schedules events in the 'Reactive region'. We will see in few minutes what this means and how this can be used to avoid race condition.

Next: Creating Programs


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