Structure Type in SystemVerilog

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Structures and Unions in Your Design

Although structures and unions look similar, they serve two entirely different purposes.

The main purpose of structures is to help you organize and arrange a set of related variables. Consider this example where a module sender sends a PCI Express packet as its outputs. A PCI Express packet consists of 17 fields such as a 12 bit wide length, a 32-bit or 64-bit wide address, a data payload field, and so on. A traditional output port definition for this module will look as follows.

Sender module: Take 1

module sender ( 
   ...
   output bit [11:0] length,
   output bit [63:0] address,
   output bit [63:0] data_payload,
   ...
); 

However, all fields of PCI Express can be organized into three broad categories: a header (which contains length, address and 13 other fields), and a data payload. It is easy to see yu can significantly reduce the number of ports by defining a structure header as follows.

Sender module: Take 2

typedef struct header {
   bit [11:0] length;
   bit [63:0] address;
   ... 
}; 

module sender ( 
   ...
   output header h, 
   output bit [63:0] data_payload, 
   ... 
); 

Since we are at it, we might as well consider defining another structure pcie_packet that encapsulate it all.

Sender module: Take 3

typedef struct header { 
   bit [11:0] length; 
   bit [63:0] address;
   ... 
}; 

typedef struct pcie_packet {
   header h; 
   bit [63:0] data_payload;
}; 
module sender ( 
   ...
   output pcie_packet p,
   ... 
); 

No prize for guessing which one of the above looks cleanest.

A union, on the other hand, can be used to or more forms of the same variable. To continue with our last example, recall that the address field in a PCI Express packet can be either 32-bit or 64-bit. However, in all of the previous structures, address has been declared as 64-bit wide assuming 32 of those bits will remain unused. There is no other way in traditional Verilog to handle this. With the introduction of union, however, you can re-define

header as shown below.

typedef struct header {
   bit [11:0] length; 
   union { 
      bit [31:0] address_32; 
      bit [31:0] address_64; 
   } 
} 

Here, only one of address_32 and address_64 will remain valid at any given point of time.

Are They Synthesizable?

While support for SystemVerilog-specific types (including structure and union) in synthesizers have just started showing up at the time of writing this article (June, 2004), there are strong indications that they will be supported by a large number of vendors. Both structure and union are synthesizable semantically, as long as you obey certain rule in coding them (no variable part-select etc.). If your synthesis tool vendor does not support structure and union, let them know that you want it.

Postscript 06/30/2004: Steve Smith from Synopsys informed us that "...the SystemVerilog Structures are synthesizable by (Synopsys) Design Compiler (from version 2003.12)."

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