SystemVerilog Assertion

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The 'expect' Statement

An expect statement is very similar to an assert statement, but it must occur within a procedural block (including initial or always blocks, tasks and functions), and is used to block the execution until the property succeeds.

   task mytask;
   ...
   if (expr1) 
      expect (my_property) 
         pass_block();
      else // associated with the 'expect', 
           // not with the 'if'
         fail_block();
   ...
   endtask

Unlike an assert statement, an expect statement starts only a single thread of evaluation. It comes out of the blocking mode only if the property succeeds or fails.

The 'bind' Directive

It is sometimes desirable to physically separate a property (which is primarily a verification entity) from a design (whose primary objective is to translate itself to a working silicon). A bind directive can tie them together even though they are in two separate files.

A bind directive can tie a module, an interface or a program instance with a module or module instance and can be specified in a module, an interface, or a compilation-unit scope. A property can be specified within a module differnt from the design module. These modules can then be tied together using a bind directive. The following example shows how to do it. Let us assume design_module_1 is the instance of a design module design_module.

 
   bind design_module prop_module prop_module_1 (arg1, arg2, ...);
   bind design_module_1 prop_module prop_module_1 (arg1, arg2, ...);

With this, we conclude our discussion on SystemVerilog Assertion. SystemVerilog Assertion combines many new and useful features together and it is our hope that this tutorial has helped you to see how these features can be useful for your design verification. At Project VeriPage we are always looking out for your feedback. So do not hesitate to send us your experience, example and lessons learnt from your own SystemVerilog Assertion project at article@project-veripage.com.