SystemVerilog Assertion

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Concurrent Assertion

Immediate assertions are quick and easy way to create an assertion and are roughly equivalent of VHDL assert statement. However, the real power of SystemVerilog assertions lies in its ability to define concurrent assertions. While an immediate assertion describes a logic behavior at an instant of time, a concurrent assertion detects a behavior over a period of time.

Concurrent assertion are also different from immediate assertion in another important aspect. While expressions for an immediate assertion is event driven and evaluated whenever a variable in the expression changes value, evaluation for a concurrent assertion is associated with a clock edge and is done right before the clock edge. (More precisely, the values of variables used in a concurrent assertion are sampled in the Preponed region of a time slot and the assertions are evaluated during the Observe region. Both these regions occur immediately before a clock edge). Evaluating an assertion just before a clock edge also ensures that all variables have attained their stable and race free values.

The third difference between immediate and concurrent assertion is that an immediate assertion occurs within a procedural block (an initial or always block). A concurrent assertion can occur within a procedural block or within a module (same way that an assign, always or initial block is instantiated).

Since concurrent assertions are associated with clock edges, their timing model is based on 'clock ticks'. A clock tick represents an active edge of a clock and the time interval between two clock ticks is the active period of the associated clock.

 
if (Sequence 1 occurs followed by Sequence 2) 
   execute pass_block;
else 
   execute fail_block;

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