SystemVerilog Assertion

Part 1: The Ground Work

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Layers of Concurrent Assertion

A concurrent assertion can be thought of consisting of several layers of abstractions. Take our previous case for example.

  • First we need to evaluate individual expressions that make up Sequence 1 and 2. For instance, in order to detect Sequence 1, we must evaluate (~reset) i.e., the de-assertion of reset signal and then (req) or the assertion of the reset signal. Similarly for Sequence 2, we must evaluate (ack). A boolean expression is the most basic layer of any concurrent assertion.
  • Once the expressions are evaluated, the next step is to evaluate the sequence that these expressions are part of. So, Sequence 1 can be expressed as: (~reset) ...[wait for five clocks]...(req). A sequence is the next layer of abstraction in concurrent assertion. At this point, you should also note that Sequence 1 and Sequence 2 could have been combined into one longer sequence of events and that would not have made any difference in the overall task that this assertion wants to achieve.
  • Once you have both the sequences defined, the next step is to define a property which is essentially what our previous pseudo-code defined. It makes use of Sequence 1 and 2 defined in a lower layer and associates a pass or fail block to their combined value.
  • The top-most layer of abstraction for concurrent assertion is the assertion directive layer where a property is associated with a specific block of code with a clear intention of its instantiation (detecting an illegal sequence or measuring coverage for example).
These four layers are illustraed in Figure 1 below.

Assertion Directive Layer

Property Specification Layer

Sequence Layer

Boolean Expression Layer
Figure 1. Abstraction Layers of Concurrent Assertions
Knowing about concurrent assertions is essentially same as knowing about these four layers.

Boolean Expression Layer

The most elementary layer of concurrent assertion, the boolean layer evaluates a boolean expression to be either true or false. If the sampled value of the expression is 1, the expression is true. If the value is one of 0, X or Z, the expression is false.

There are certain restrictions on the type of variables that you can use in a boolean expresion. For example, the following types are not allowed in a boolean expression.

  • shortreal, real and realtime
  • string
  • event
  • chandle
  • class
  • associative array and
  • dynamic array

You can use a function in a boolean expression, but it can not have an output or ref argument, nor can it have any side effect. Also prohibited are assignment operators (+= or -=) and unary increment/decrement (++ and --) operators, to prevent side effects.

Summary of Part 1

In this Part 1, we learnt about what assertions are and what they are for. In SystemVerilog, assertions can be either immediate or concurrent, based on whether they are executed at a given instant of time, or over a period of time. While concurrent assertions are easy to build, the real power of SystemVerilog assertions are in its concurrent part. In this part, we saw the four layers of SystemVerilog concurrent assertions. We looked into the most basic of these layers - the Boolean Expression Layer. In the Part 2 of this series, we will delve into possibly the most complex of all the layers - the Sequence Layer.

Prev: Concurrent assertion | Next: The Sequence Layer


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