Here are some of the Verilog vendors. This list, by no means, is exhaustive and purely based on their popularity rather than their usefulness or efficiency.

Simulators

Mentor Graphics: Mentor Graphics ModelSim came from Model Technology. ModelSim is a popular simulator for some users, particularly those who use PCs for simulation.

Cadence Design Systems : Verilog-XL, the first Verilog Simulator, retained its popularity for many years. Cadence has stopped adding new features to XL for a long time now, but somehow many people still like it. Cadence also has NC Verilog, which is a compiled Verilog simulator. Verilog-XL and NC-Verilog were the first commercial simulators to support both PLI1.0 and PLI2.0 of IEEE Std.1364-1995 Verilog.

Viewlogic (now part of Synopsys ) came up with the first compiled (i.e. not interpreted) version of Verilog, called VCS and it turned out to be 3-4 times faster than Verilog-XL. Since then their race against time is on and God knows where they will end up. VCS does not support PLI2.0 yet, and more than that it is still unknown whether they will ever support it.

SpeedSim came up with yet another kind of Simulator (apart from interpretive event-driven and compiled event-driven), known as cycle based simulators. This class, by their very nature, is very fast (around 10 times than others), but the catch is that the simulation is done only at certain edges of specified set of signals.

Waveform Viewers

Design Accelaration Inc's Signalscan is a complete platform for debugging and signal viewing. Ideawise it is pretty cool. Their waveform viewer is one of the bests in the industry, but one wishes that one could say the same about their debugging utilities.

Veritools Inc came up with one of the first waveform tools in the industry - Undertow.

Hardcopy stuff

Accellera is a non-profit organization, which is dedicated for HDL related development. You can purchase their version of Verilog Language Reference Manual (now in its second version) and PLI reference manuals. Accellera is also the organizing body for SystemVerilog 3.0, 3.1, 3.1A and 3.1AE development. The LRMs for SystemVerilog can be obtained from here.